|Working to extend Moore's Law into the future, researchers have developed a new configuration of a nanowire field-effect transistor or, “gate-all-around” transistors that has the promise to shrink microelectronics even further..|
esearchers working in France report the creation of a nanowire transistor that could be scaled down to to power the microprocessors of the 2020s, extending Moore's Law another decade.
The technology that will power this improvement is known as nanowire field-effect transistors or FETs.
In these nanoscale devices, current flows through the nanowire or is pinched off under the control of the voltage on the gate electrode, which surrounds the nanowire. Hence, nanowire FETs’ other name: “gate-all-around” transistors.
Due to their small size, single nanowires cannot carry enough current to make an efficient transistor however.
The new research showed a solution is to make a transistor that consists of a small forest of nanowires that are under the control of the same gate and so act as a single transistor
Researchers working in France, Guilhem Larrieu of the Laboratory for Analysis and Architecture of Systems, in Toulouse, and Xiang‑Lei Han of the Institute for Electronics, Microelectronics, and Nanotechnology, in Lille, report the creation of a nanowire transistor that can be scaled down to perform the task.
Their transistor is made up of an array of 225 doped-silicon nanowires, each 30 nm wide and 200 nm tall, vertically linking the two platinum contact planes that form the source and drain of the transistor. Besides their narrowness, what’s new is the gate: A single 14-nm-thick chromium layer surrounds each nanowire midway up its length.
The nanowires were of an unusual construction. Unlike with most vertical nanowire transistor prototypes, in which the nanowires are grown upward from a substrate, the French duo created their nanowires by starting out with a block of doped silicon and then etching away material to leave nano pillars. In between the pillars, they deposited an insulating layer to about half the pillars’ height.
Then they deposited the 14 nm of chromium and filled the remaining space with another insulating layer. “We tried to make the process completely compatible with current technology used in electronics. No new machines will have to be invented,” says Larrieu. The researchers have plans to try to go below 10-nm gate length, and also to use indium gallium arsenide nanowires because of the better electron mobility.
Gate-all-around technology is now under study at a number of university labs worldwide and the verdict has not been finalized on the ability of FET's to extend Moore's Law, however the research is promising.
SOURCE IEEE Spectrum
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